|Table of Contents|

Realization of Hardware Algorithm of Improved Bit Level Median Filtering
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《哈尔滨理工大学学报》[ISSN:1007-2683/CN:23-1404/N]

Issue:
2015年03期
Page:
35-039
Research Field:
计算机与控制工程
Publishing date:

Info

Title:
Realization of Hardware Algorithm of Improved Bit Level Median Filtering
Author(s):
HAN Jian一hui GE Wei
(School of Computer Science and Technology,Harbin University of Science and Technology,Harbin 150080,China)
Keywords:
median filteringsaltnoiseand pepper noiseFPGAmodelsim
PACS:
TP39
DOI:
-
Abstract:
In order to reduce hardware resources occupation and improve the filtering speed,paper introducedan improved bit level median filter design and used this bit level median filtering to construct a 3*3 template improved bit level median filtering module. Then the 3 x 3 template improved bit level median filtering module wasapplied to reduce the salt and pepper noise of the gray image. This paper focused on the design of the improved bitlevel median filtering and the improvement of the seeking the most value calculating module. The whole design wasbased on FPGA and by simulation of the ModelsimSE 10. 1 a software. The data of experiment proved that the improved bit level median filter can greatly reduce the consumption of hardware resources,and it can complete a fastbit level median filtering and output results in one clock cycle.

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Last Update: 2015-08-24